Integrated circuits (IC), including application specific integrated circuits (ASIC), are increasing in processing capability and are shrinking in physical size. Smaller ICs contain added components such as digital receiving and processing a devices. Decreasing the size of ICs has led to an increase in IC processing speed since communication paths are decreased between IC components.
As IC size decreases, however, resistance-capacitance (RC) time delay of metal interconnects between IC components begins to limit IC performance. Interconnect RC time delay is associated with metal resistance of interconnections and capacitance associated with dielectric media. Because metal resistance and dielectric media are inherently part of the materials used in construction of an IC, only a change in materials will affect (improve) RC time delay. A change in materials may be technically impossible or cost prohibitive.
Differences in propagation delay, when compounded across all interconnections, such as clock nets or paths, in a complex IC may lead to unacceptable degradations in overall system-timing. This problem is often referred to as “clock skew.”
FIG. 1 illustrates a clock tree that distributes clock signals in a controlled manner. An IC may contain numerous clocked components requiring clock signals. A clock tree or similar clock architecture provides the necessary clock signals to the components. Components within an IC, specifically registers of the components, may require that the clock signals be synchronized. To be considered “synchronized,” clock signals have the same phase at different receivers, despite propagation delays.
In this particular example, clock receiving components 10, 15, 20, and 25 reside on a single IC. Components 10, 15, 20, and 25 may be at varying distances from one another. In other words component 10 may be an unequal distance from component 15, as component 15 is to component 20. Oftentimes, due to IC design constraints or physical architecture restrictions on an IC, components must be placed at varying locations at varying distances from one another. In this example, components 10, 15, 20, and 25 are components that must be synchronized with one another (i.e. have the same phase clock signals). Further, since components 11 are placed at varying distances from one another, components may also be located at varying distances from a clock source such as clock driver 30. Since clock signals travel over varying distances from the clock source to the components, assuring that each clock signal is in phase with the other clock signals becomes a complicated task.
In typical clock architectures such as the clock tree of FIG. 1, a controller such as controller 35 initiates a clock signal. Controller 35 can be located on an IC (on-chip) or external to an IC (off-chip). Controller 35 instructs clock driver 30 to generate a clock signal. Clock driver 30 may be implemented for example as a clock oscillator or clock generator or similar component. Alternatively, clock driver 30 may be a clock buffer. A clock signal transmitted by clock driver 35 is passed on to fan-out clock drivers 40, 45, 50, 55, 60, and 65. All clock signals derived from clock driver 30 have the same frequency, although clock signals arriving at various components or registers may have different phase values.
To assure that the clock signals arriving at components 10, 15, 20, and 25 are properly synchronized and have the same phase, paths 70, 75, 80, and 85 must have approximately the same length and propagation delay characteristics. If components 10, 15, 20, and 25 are not located equidistant from their respective clock drivers 50, 55, 60, and 65, certain paths may have to be wrapped around to assure equal lengths and propagation characteristics of all paths. When IC space is at a premium, this approach may not be feasible.